1. Field of the Invention
The present invention relates to semiconductor voltage generator circuits, and particularly to capacitive voltage multiplier circuits.
2. Description of the Related Art
Many integrated circuits, particularly those, using a single power supply voltage, incorporate on-chip circuitry to generate a xe2x80x9cboostedxe2x80x9d voltage having a magnitude greater than the power supply voltage. Frequently this boosted voltage is used as a veritable power supply voltage for portions of the circuitry contained on the integrated circuit. For example, certain types of semiconductor memories, such as xe2x80x9cflashxe2x80x9d EEPROM memories, write a memory cell by accelerating electrons across a tunneling dielectric and storing the charge on a floating gate above a field effect transistor. On contemporary devices, this acceleration of charge across the tunneling dielectric frequently requires a xe2x80x9cwrite voltagexe2x80x9d on the order of 8 volts, yet the remainder of the operations of the memory circuitry typically requires a voltage on the order of only 3 volts, including reading the memory cells. Unlike many older devices which require two different power supply voltages be supplied to operate the device (e.g., +5 and +12 volts), many contemporary devices require only a single power supply voltage (usually called VDD) equal to 2.5-3.3 volts (relative to xe2x80x9cgroundxe2x80x9d or VSS). This VDD power supply voltage is typically utilized to power most of the device, including the normal read operation circuits. The write voltage (frequently, although not always, called VPP for legacy reasons) is generated by an on-chip voltage generator having a typical value of +8 volts (again relative to VSS) rather than requiring a separate power supply voltage be supplied by a user of the device.
In many integrated circuits, such on-chip voltage generators are implemented as capacitive voltage multiplier circuits, largely because of the historical ease of monolithicly implementing suitably large capacitors, especially compared to monolithicly implementing good quality inductors. These capacitive voltage multiplier circuits are usually called xe2x80x9ccharge pumpsxe2x80x9d by those in the art. Not to be confused with capacitive voltage multiplier circuits, there is another class of circuits also frequently called charge pumps. These are frequently used to integrate small current pulses generated each cycle by a phase detector circuit, and to consequently generate an analog voltage on a capacitor node which represents the phase error between two phase detector input signals. During each cycle, a typical phase detector xe2x80x9cpumpsxe2x80x9d a first current pulse into the capacitor node and xe2x80x9cpumpsxe2x80x9d a second current pulse from the capacitor node. If the phase error is zero, these two current pulses are equal, and the voltage on the capacitor node is unchanged. But if the phase of one input signal lags the other, one of the current pulses is greater in magnitude, or longer in duration, or both, so that the net charge into the capacitor node is non-zero, and a voltage change results. Such xe2x80x9cphase detector integratorxe2x80x9d charge pumps are quite different in both function and structure, and are consequently not considered to be related to capacitive voltage multiplier circuits. Consequently, as used herein, a xe2x80x9ccharge pumpxe2x80x9d refers to a capacitive voltage multiplier circuit and not to such phase detector integrator circuits, unless the context so requires.
In the nonvolatile memory example described above, the write voltage generated by the charge pump is higher than the VDD power supply voltage provided to the device. In other integrated circuits, a charge pump is frequently used to generate a voltage below the reference voltage VSS (i.e., xe2x80x9cbelow groundxe2x80x9d). For example, a negative bias voltage is generated in many memory devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and other circuits, to bias a substrate and/or a CMOS well within the substrate. Charge pumps for such purposes have been used for over twenty years.
Referring now to FIG. 1, a schematic diagram of a traditional (and very well known) charge pump circuit for generating a boosted voltage above VDD is shown, which circuit is taught by John F. Dickson in xe2x80x9cOn-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique,xe2x80x9d IEEE Journal of Solid State Circuits, Vol. SC-11, No. 3, June 1976, pp. 374-378. The charge pump 100 includes a plurality of serially-connected charge pump stages, one of which is labeled 102. Each charge pump stage includes a diode, such as diode 104, and a pump capacitor, such as capacitor 106, and has an input node, such as node 108, and an output node, such as node 110. A complementary pair of clock signals CLK and /CLK (labeled in the figure as CLK xe2x80x9cbarxe2x80x9d with the traditional inverting xe2x80x9cbarxe2x80x9d over the name) are provided to drive the various pump stage capacitors. Odd-numbered (or alternately even-numbered) pump stages are driven by the CLK signal, while even-numbered (alternately odd-numbered) pump stages are driven by the /CLK signal. The input node of the first serially-connected charge pump stage, here labeled as node 111, is usually connected to the VDD power supply. A final isolation diode 114 may be considered as part of the last serially-connected charge pump stage, and the output voltage of the charge pump 100 taken from node 116 rather than from node 112 (which would otherwise be considered the output node of the last serially-connected charge pump stage).
The complementary clock signals may be overlapping or non-overlapping clock signals, and are usually driven with full VDD-level swings (i.e., transitioning between a low level of VSS and a high level of VDD). Consequently, each charge pump stage boosts the voltage conveyed to its input node by an amount equal to VDD less a diode drop (assuming relatively negligible DC current and ignoring second order effects). Including the effect of the last isolating diode 114, the maximum theoretical output voltage achievable from such a charge pump 100 is equal to VDD(N)xe2x88x92VDIODE(N+1), where N is the number of charge pump stages and VDIODE is the forward diode drop. In practice, the diodes are frequently implemented as diode-connected FETs (field effect transistors), and the capacitors implemented as large FETs, each with its source and drain terminals connected together to form one terminal of the capacitor, and its gate terminal forming the other terminal of the capacitor. Furthermore, the output voltage is usually somewhat less than this theoretical value, due to stray capacitances, incomplete charge transfer, DC current flow provided into the output node, and other effects, which have been well studied in the literature.
While on-chip voltage generator circuits may relieve a user from supplying a second power supply voltage, such circuits frequently require a significant amount of layout area to implement, which may increase die size substantially, and consequently increase costs. Moreover, such voltage generator circuits also may consume a significant amount of power relative to the remainder of the circuit, and thus increase the current that must be supplied by the user (e.g., by the VDD power supply). Any increase in power dissipation may also increase the temperature of the die during operation. In a battery-powered environment, any increase in power consumed by a device may have significant implications for battery life, and any additional heat generated may also be difficult to dissipate. Consequently, continued improvements in charge pump circuits are desired.
Traditional charge pump circuits utilize a plurality of serially-connected pump stages, which are driven by clock signals of identical amplitude. This results in a uniform additional voltage contributed by each pump stage, and an output voltage which is generally a multiplicative function of the number of pump stages. If instead the clock signals increase in amplitude for each successive pump stage, the additional voltage contributed by each successive pump stage increases for each such successive pump stage. An exemplary charge pump circuit in accordance with the present invention provides with each successive pump stage an output voltage that is a multiple, although not necessarily an integral multiple, of the input voltage for the stage. Consequently, the output voltage achieved by such an exemplary charge pump circuit is an exponential function of the number of pump stages within the charge pump circuit.
Many particular circuit arrangements of pump stages are contemplated by the present invention, including pump stages responsive to a single clock, as well as others that are responsive to a complementary pair of clock signals. Moreover, other embodiments of the invention include pump stages that lose a diode drop with each stage, as well as those pump stages that xe2x80x9cfully chargexe2x80x9d an associated capacitor and thus do not lose any diode drop per stage.